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職務說明：
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1.Cooperate with IC project leader, design team to implement digital RTL code and verify, guarantee the digital block function and spec.
2.Independently specify, design, implement, verify hardware re-usable HDL modules optimized for structured ASIC or FPGA device architectures.
3.Ownership of the RTL to physical design flow including Synthesis, and the development of automation scripts.
4.RTL implementation of I/O, clock, reset, BIST, DFT & JTAG structures or others.
5.Timing constraint development and signal integrity based timing analysis/closure.
6.Work with RTL and physical design teams to define clock/reset distribution, floorplan, I/O pad ring, and package pin outs.
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職缺名稱：
E-mail：